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A survey of digital circuit testing in the light of machine learning

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Abstract The insistent trend in today's nanoscale technology, to keep abreast of the Moore's law, has been continually opening up newer challenges to circuit designers. With rapid downscaling of integration, the intricacies involved in the manufacturing process have escalated significantly. Concomitantly, the nature of defects in silicon chips has become more complex and unpredictable, adding further difficulty in circuit testing and diagnosis. The volume of test data has surged and the parameters that govern testing of integrated circuits have increased not only in dimension but also in the complexity of their correlation. Evidently, the current scenario serves as a pertinent platform to explore new test solutions based on machine learning. In this survey, we look at various recent advances in this evolving domain in the context of digital logic testing and diagnosis. This article is categorized under: Algorithmic Development > Structure Discovery Technologies > Machine Learning Technologies > Prediction
Digital circuit testing. (a) Canonical structure of a digital circuit (Abramovici et al., 2002). (b) Test application of input patterns generated by ATPG, to a chip in the ATE (Bushnell & Agrawal, 2005)
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Network architecture of GCN. Node embeddings are generated in Layer 1 and Layer 2. The fully connected (FC) third layer execute nodes classification (Ma et al., 2019)
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A combinational circuit showing an X‐source (blue), the three partitions (blue), (brown), (green), and the gates directly fed by the X‐source (red) (Pradhan et al., 2019)
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Illustration of the PRPG‐selection method (Li et al., 2017)
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An illustration of the ANN architecture used by Zhang et al. (2011)
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Defect classifier (L. R. Gómez & Wunderlich, 2016)
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Flow for the classification of bridging defects (Nelson et al., 2010)
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Three‐output classifiers where X is a feature vector with d elements, and y1, y2, and y3 are discrete variables denoting the classes (Huang et al., 2018)
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An example of CGNN training‐vector (Chern et al., 2019)
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Compressing binary failure vectors into an “integer failure vector” (Chern et al., 2019)
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Automated die‐inking (Xanthopoulos et al., 2017)
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Yield learning phases (Hora, Segers, Eichenberger, & Lousberg, 2002)
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Multiple scan with response compactor (Mitra & Kim, 2002)
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Intersecting output cones of two faults. O1, O12, and O2 are the set of output ports reachable from only f1, both f1 and f2 and, only f2, respectively
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Technologies > Prediction
Technologies > Machine Learning
Algorithmic Development > Structure Discovery

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